]> code.citadel.org Git - citadel.git/tree - citadel/modules/vcard/
Made the RBL evaluation conditional cleaner by assuming short-circuit evaluation.
[citadel.git] / citadel / modules / vcard /
drwxr-xr-x   ..
-rw-r--r-- 4 .gitignore
-rw-r--r-- 34465 serv_vcard.c